The present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of improving system memory bandwidth utilization during graphics translational lookaside buffer cache miss fetch cycles.
The main memory in many of today""s computer systems includes a space used by the graphics subsystem. Typically, the computer system""s processor and graphics controller have access to the graphics portion of main memory. A memory controller controls access to the main memory. The memory controller includes an arbiter that serves to arbitrate access to main memory. The memory controller also typically includes a graphics translational lookaside buffer (GTLB). Whenever an access to the graphics portion of main memory is requested by either the processor or the graphics controller, a translation must take place between the virtual address included in the access request and a corresponding physical address. This translation is typically handled by the GTLB.
The GTLB includes a cache that stores some of the most recently used physical addresses in the hope that future virtual addresses received as part of graphics memory access requests will correspond to physical addresses stored in the GTLB cache. Whenever a graphics memory access request misses the GTLB cache, or in other words the access request includes a virtual address that does not correspond to any of the physical address presently stored in the GTLB cache, the GTLB must fetch the appropriate physical address from a table located in main memory. Once the physical address is fetched and stored in the GTLB cache, the graphics memory access request can continue and is issued to a memory interface that handles the transaction with the main memory.
Today""s main memories are typically capable of pipelined operation. That is, several main memory accesses may be pending at any given time. In prior memory controllers, whenever there is a GTLB cache miss, and therefore a GTLB fetch cycle, all main memory requests received after the access request that caused the GTLB fetch cycle are stalled until the fetch cycle is complete. This means that the high bandwidth main memory interface is left to handle a single fetch transaction, and the bandwidth normally available when using pipelined transactions is wasted. As main memory interfaces become more and more sophisticated and capable of sustaining greater bandwidth, the penalties associated with stalling the main memory interface for a GTLB fetch cycle will increase.
A method and apparatus for improving main memory bandwidth utilization during graphics translational lookaside buffer fetch cycles is disclosed. The apparatus includes a first request path and a second request path. The apparatus further includes a graphics translational lookaside buffer that includes a cache. The graphics translational lookaside buffer issues an address fetch request to a memory interface when a graphics memory request received from the first request path or from the second request path misses the cache. The apparatus also includes a memory arbiter that includes a first request path cycle tracker and a second request path cycle tracker. The memory arbiter allows a request received from the second request path to be issued to the memory interface when a graphics memory request received from the first request path is stalled due to a graphics translational lookaside buffer cache miss.